1. Field of Invention
The present invention relates to a testing and packaging process. More particularly, the present invention relates to a wafer level testing and bumping process.
2. Description of Related Art
Following the rapid development of semiconductor fabrication techniques, advanced and precise semiconductor devices are now being produced to meet the increased demand in many electronic products. In general, for the fabrication of semiconductors and the subsequent package/test, a front stage fabrication process is carried out after the design of the integrated circuit (IC). The front stage fabrication process includes fabricating integrated circuits on a wafer followed by testing the circuits. After sawing the wafer into individual chips, a wire bonding or a flip-chip bonding process is usually carried out to connect bonding pads on the active surface of the chip with contact pads on a carrier. The carrier is a substrate or a lead frame, for example. Using a flip-chip package as an example, a plurality of bonding pads is formed on the active surface of the chip prior to attaching a bump to each bonding pad. Hence, the bonding pads on the active surface of the chip are electrically and mechanically connected to contact pads on the substrate through the bumps. In other words, electrical signals can be transmitted from the chip to an external electronic device and vice versa through the carrier.
FIG. 1A is a top view showing the layout on the active surface of a conventional wafer. FIG. 1B is a cross-sectional view along line I—I of FIG. 1A. FIG. 1C is a cross-sectional view along line II—II of FIG. 1A. As shown in FIGS. 1A and 1B, the wafer 100 has an active surface 102. Typically, the active surface 102 refers to an area on the wafer 100 where active devices 104 are formed. The active devices 104 connect with each other as well as flip-chip bonding pads 108 through metallic interconnects 106. According to the actual electrical function, the flip-chip bonding pads 108 can be subdivided into signaling contacts, power source contacts or ground contacts. Using a flip-chip bonding wafer 100 as an example, a passivation layer 110 is usually formed over the active surface 102 of the wafer 100 before performing the bumping process. The passivation layer 110 covers fuse lines 112 and fuse windows 114 but exposes the flip-chip bonding pads 108. The bumps 120 are formed over the respective flip-chip bonding pads 108 for connecting electrically with the contacts on an external electronic device (not shown).
To test the integrated circuits within the wafer 100, the flip-chip bonding pads 108 or the bumps 120 on the active surface 102 are used as testing points after the metallic interconnects 106 inside the wafer 100 are formed as shown in FIG. 1B. Note that a vertical probe card 10 with an array of probe pins 12 that correspond in positions with the top ends of the bumps 120 is used to test the wafer 100 so that any problems within the wafer 100 can be found through a circuit analysis.
After performing a detailed analysis of the internal circuits inside the wafer 100, the mal-functioning portion of the integrated circuit can be repaired by cutting a corresponding fuse line 112 using a laser beam and replacing the defective circuit with a backup circuit as shown in FIG. 1C. Thus, a conventional wafer 100 is usually designed with a few backup circuits and fuse lines 112. The fuse windows 114 is a special design for decreasing the thickness of the section on top of the fuse line 112 so that the cutting of the fuse lines 112 and the replacement of the defective circuit with a backup circuit is facilitated. Note that thickness of the structure on top of the fuse line 112 must be reduced to facilitate the passage of a laser beam to the fuse line 112 and repair the defective circuit. Thus, a portion of the passivation layer 110 can be removed prior to repairing the defective circuit so that the fuse window 114 is exposed and thickness of the structure above the fuse line 112 is reduced. Thereafter, a laser beam is aimed to cut out the fuse line 112 and then another passivation layer 110a is formed to cover the aforementioned fuse window 114. However, in the process of repairing the defective circuit, holes for exposing the fuse windows 114 must be opened up in the passivation layer 110a anew so that thickness of the local structure above the fuse line 112 is again reduced. Hence, the process cycle for testing and packaging the wafer 100 is longer.
FIG. 2 is a flow chart showing the steps in a conventional method of testing and packaging a wafer. As shown in FIGS. 1B, 1C and 2, a plurality of flip-chip bonding pads 108 are formed on the active surface 102 of the wafer 100 in step S11. Thereafter, in step S12, at least one fuse window 114 is formed on the active surface 102 of the wafer 100. In step S13, a passivation layer 110 is formed over the active surface 102 of the wafer 100. The passivation layer 110 exposes the flip-chip bonding pads 108. In step S14, a bumping process is carried out to form a bump 120 on each flip-chip bonding pad 108. In step S15, the wafer 100 is electrically tested using the bumps 120 as test points. In step S16, a portion of the passivation layer 110 is removed to expose the fuse window 114 and hence relative thickness of the structure above the fuse line 112 is reduced. In step S17, a laser beam is deployed to cut the fuse line 112. In step S18, a dielectric material is deposited to fill the fuse window 114. Note that the fuse window 114 exposed after locally removing a portion of passivation layer 110 must be refilled afterwards. Therefore, the number of processing steps is increased resulting in an extension of the production cycle and an increase in the production cost.
Furthermore, as shown in FIG. 1B, the average deviation of the bumps 120 from a coplanar surface after a reflow process is about 50 μm. Thus, to ensure a clear and accurate testing, the force acting on the vertical probe card 10 must be increased so that sufficient pressure is produced to make the tips of all probe pins 12 have contact with the bumps 120. However, excessive pressure on the probe pin 12 on the probe card 10 will lead to over-travel, a phenomena that will damage the internal circuit of the wafer 100 and, in some cases, lead to a mal-functioning of the wafer 100.